On the Bend Minimization in Clock Tree Networks

Vias in Clock Distribution Networks (CDNs) are one of the major sources of signal degradation and delay uncertainty. Also they may impact circuit reliability due to their sensitivity to process variations. With feature size reduction these variations will manifest themselves in adverse effects on clock skew and clock jitter. Therefore, via reduction becomes one of the challenging research areas in high performance digital systems. In this paper we propose an algorithm which minimizes the number of bends that is closely related to number of vias. The proposed algorithm is able to construct a zero skew clock tree with at most one bend branch merging. Pruning some Steiner loci which may cause extra bends, the algorithm effectively reduces the number of bends and achieves a zero skew clock tree with uniform distribution of bends at the expense of small increase in wire length. Experimental results show the proposed algorithm reduces the number of bends by an average of 15.6% with an increase of 0.8% in total clock tree wire length in comparison to the Differed Merged Embedding, DME, algorithm.